Field of the Invention
The present invention is directed in general to integrated circuit devices and methods for manufacturing and operating same. In one aspect, the present invention relates to the manufacture and use of semiconductor devices having a test mode operation.
Description of the Related Art
Testing of integrated circuit devices is a challenging task that requires significant cost, time, and equipment to test functionality and timing of circuits in each integrated circuit device. Integrated circuit devices often include a test mode to reduce overall test time and to test embedded functions not available at a package pin. To minimize or eliminate inadvertent entry into the test mode, test mode entry circuits typically require specified test mode entry actions, but such circuits can still be susceptible to noise or power-down and power-up sequences.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.